Thermal imaging can be a very powerful tool for semiconductor failure analysis. Current leakage defects typically generate thermal hot-spots: metal short circuits, latch-up, junction defects in diodes and transistors, breakdown of MOS gate oxide, ESD failures, etc. When using conventional thermography or thermal imaging on semiconductor devices, we are faced with two problems:
When using a thermal camera to inspect semiconductor devices, one can see a contrast in the infrared image even when no bias voltage is applied, i.e., the device or wafer is at a uniform temperature. This contrast is caused by differences in emissivity of the materials in the semiconductor device, as shown in Figure 1 as an example.
The high thermal conductivity of silicon causes low thermal gradients across powered devices. Heat sources in silicon are often imaged as a large blob. The sensitivity of the camera also picks up the changes in emissivity with the temperature of the different materials in the device. This shows up as an image of the device in the thermal emission image, despite background correction between a powered and unpowered state of the device.
Thermal hot spot dilation is heat spreading from the defect location. The problem with thermal hot spot dilation is even more acute when a point heat source is located below the surface, i.e., when imaging through the silicon substrate. The thermal hot-spot is ‘lost’ within a larger dilated area.
Lock-in thermal imaging uses pulsed electrical stimulation on the semiconductor device, and a thermal camera, synchronized to the timing of the power supply, to minimize thermal hot spot dilation. Lock-in thermal imaging results in improved defect localization accuracy and thermal sensitivity.
Moreover, phase delay information from thermal lock-in analysis (thermal time delay will cause a phase shift, see Figure 2 and Figure 3) can be used to determine the location of a hot spot or failure in a 3D structure of stacked integrated circuits. As shown schematically in Figure 2, conventional thermal imaging methods would be unable to distinguish differences in depth location between the two heat points (or failure sources).
Figures 4 and 5 show an example of lock-in thermal imaging (without using any phase information). Figure 4 is the thermal lock-in image and it shows the faint signal of a hot spot dissipating 2 μW of power (device is biased at 1 V and 2 μA). Figure 5 is the overlay image – thermal emission (from lock-in image, and in pseudo-color and after thresholding) is superposed on a thermal background image.
The above example demonstrates the value and effectiveness of using thermal lock-in when conducting semiconductor inspections. The ability to localise defects reduces the time required for failure analysis engineers to identify and rectify the issue. The overall efficiency of a wafer level inspection process is improved thanks to thermal lock-in enabled by the Xenics XCO 640 camera module. The XCO camera module is used in the SEMICAPS SOM5000 Tester Docked Wafer Prober Thermal Microscope System.
The XCO 640 is based on a cooled MWIR engine that offers the following advantages:
The XCO 640 camera module is also used in the Xenics Tigris camera family for scientific applications. The Tigris camera comes with a compact housing, a bayonet mount for a range of standard (non-microscope) lenses and a filter wheel.